1. Field of the Invention
The present invention generally relates to a semiconductor process, and more particularly, to an exposure method suitable for a photolithography process.
2. Description of Related Art
Along with rapid progress of semiconductor process technology, further advancement in the operation speed and efficiency of semiconductor devices is demanded, which needs continuously increased compactness of a whole circuit component to increase the integration thereof. In general, in designing compact semiconductor devices, the photolithography process plays a significant role in the entire process.
In a semiconductor process, the patterning of film layers or doping are performed by using a photolithography process to define a desired region. The photolithography process is performed by forming a photoresist layer on the surface of a wafer, followed by conducting a photoresist exposure step and a developing step, so as to transfer the mask patterns onto the photoresist layer to obtain a patterned photoresist layer.
Among the vital factors affecting a photolithography process, in addition to critical dimensions, the most important factor is alignment accuracy. In particular, to meet the higher and higher device integration today, the pre-exposure wafer alignment is more important. A semiconductor device usually needs a plurality of photolithography processes to be completed, and therefore, to correctly transfer mask patterns onto a wafer, the alignments between a work layer with other layers on the wafer must be done before conducting each photoresist exposure step of photolithography. Thus, degradation of the yield on wafer due to inappropriate pattern transfer can be avoided and even scrapping of an entire batch of wafers can be prevented.
The conventional wafer alignment step is usually conducted by an employed exposure apparatus itself, followed by using the data of the wafer alignment to calibrate the exposure apparatus for conducting a successive photoresist exposure step. Since an exposure apparatus is unable to simultaneously conduct wafer alignment step and photoresist exposure step to meet the mass production requirement, the throughput of an exposure apparatus is much limited. In particular, along with an continuously enhancement of device integration, more alignment marks measured on a same wafer are required to provide successive data for calibrating the exposure apparatus, which makes the situation of low throughput more serious.
In addition, in order to improve the above-mentioned low throughput problem of photoresist exposure, during conducting an pre-exposure alignment step with an exposure apparatus, it is very common to conduct alignment merely on a wafer chosen from a batch of wafers or several batches of wafers and then to calibrate the exposure apparatus by taking the alignment result obtained from aligning a single wafer as the base to align all wafers of a batch or several batches, which may more affect the alignment accuracy. Since the accuracy in transferring a mask pattern onto the wafer is significant which directly affect the quality of a semiconductor process, how to effectively increase the throughput and promote the alignment accuracy to ensure higher quality of a photoresist pattern becomes one of important issues for the related manufactures to solve.